Image processing can be used to apply special effects such as changes in size, position and/or perspective to an image. Such effects cannot be achieved realistically simply by moving image data around in a memory. In order to achieve realism it is often necessary to apply complex filtering and interpolation operations to the data held in memory.
An image processing system will generally comprise a store for storing data representing pixels forming an initial image and data representing pixels forming a modified image (to which the desired effect has been applied) and a processor for the addressing and the calculation of data to create the modified image. In a so-called read-side system the processor is arranged to calculate for each pixel in the modified image the addresses in the store at which data is stored representing initial image pixels that contribute to the modified image pixel. The processor also controls the combining of the thus addressed initial image pixel data to produce the modified image pixel data. The address calculation embodies the characteristic feature of the desired effect and the data calculation is necessary in order to produce a good quality result. Both calculations are therefore important in achieving the desired result.
The data calculations are usually performed using a digital filter. Filtering is necessary to ensure that the Nyquist sampling limit is satisfied in the modified image as well as in the initial image. FIG. 16 of the accompanying drawings shows a simple example of an effect in which an initial image 150 is reduced to one quarter the size in both the x and y directions to produce a modified image 151. The graph 152 illustrates an analog representation and the graph 153 illustrates a digital representation of a line 154 in the picture 150.
The line 155 in the reduced picture 151 is one quarter the length of the line 154. However, this does not mean that the data for the line 155 can be derived by taking every fourth sample of the data 153 of the line 154. If this is done the resulting data might look something like that represented by the graph 156 which clearly does not represent the line 155. It should be noted that the horizontal axis of graphs 152 and 153 are in the same scale as the line 154 whereas the graph 156 is in the same scale as the line 155. The horizontal line of graph 156 has been enlarged in scale for the purpose of clarity. It will be appreciated that in order to obtain representative samples of the reduced image along line 155 the sampling rate must be varied to obtain meaningful samples such as shown in graph 157 (which is to the same scale as graph 156).
Visually, sampling at the wrong frequency as represented by graph 156 would be seen as aliassing artifacts in the displayed image. Such artifacts are visually unpleasant but can be avoided by limiting the bandwidth of the initial image data so that the sampling frequency for the modified image does not exceed that limit. This is achieved by performing a calculation which low-pass filters the initial image data. Such filtering will remove the high frequency components of the initial image data that cannot be recreated in the modified image data.
In addition to filtering it is often necessary to interpolate the data representing the initial image in order to obtain a modified image free from aliassing artifacts in the form of jagged edges. Interpolation is necessary because for a pixel at a given position in the modified image the corresponding position in the initial image may be at a non-integer address. Since the initial image data is defined only at integer positions, the data required for a calculation must be derived by interpolating between the data at positions either side of the non-integer address. Filtering and interpolation can easily be combined in a digital filter simply by increasing the number of and varying the values of the coefficients using the filter so as to achieve the desired effect.
It will be appreciated from the foregoing that large amounts of image data are required to be processed in order to achieve a special effect. Operators of special effects machines expect to see the desired effect instantaneously or at lest with the minimum of delay-making it necessary to process the data at high speed.
The present invention aims to provide an improved image processing system.
According to one aspect of the invention there is provided an image processing system for effecting a predetermined transformation to data representing a multiplicity of pixels which together form an initial image so as to create data representing a multiplicity of pixels which together form a transformed image in which each pixel is formed as a weighted combination of pixels in a respective block of data in the initial image, the system comprising: a controller operable for each pixel in the transformed image to identify the block of data containing all pixels in the initial image that contribute to the transformed image pixel, to divide the block into a plurality of sub-blocks and to calculate for each sub-block a set of transformation coefficients depending on the predetermined transformation; a transforming unit for applying the respective transformation coefficients to each sub-block of data in order to produce an intermediate value for each sub-block; and a register for accumulating the intermediate values from the transforming unit such that once the transforming unit has applied the transformation coefficients to every sub-block in the initial image data block the accumulated value in the register comprises the data defining the transformed image pixel.
According to another aspect of the invention there is provided a method of filtering digital data representing a first plural-dimensional array of elements to produce data representing a second plural-dimensional array of elements, the method comprising: identifying for each element of the second array a plural-dimensional block of data comprising elements in the first array that contribute to the elements in the second array; dividing the identified block of data into a plurality of plural-dimensional sub-blocks of data; calculating for each sub-block a set of filtering coefficients; applying the filtering coefficients to respective elements in the sub-block in order to produce an intermediate value for each sub-block; and accumulating the intermediate values whereby, once the filtering coefficients have been applied respectively to every sub-block of the block of data, the accumulated value comprises the data of the elements.
According to a further aspect of the invention there is provided an image processing system comprising: a random access store having an address bus and a data bus; plural independent address generators for generating addresses and outputting the same onto respective address buses; an address bus multiplexer for selectively connecting the store address bus to the generator address buses; a data bus multiplexer for selectively connecting the store data bus to a plurality of other data buses; a pluarity of independent functional units connected to respective ones of the data busses for receiving data from the random access store via the data bus multiplexer; and a control computer for controlling operation of the address generators, the address and data bus multiplexers, and the functional units so as to optimise the addressing and transferring of data within the system.
The invention also provides a memory comprising a plurality of random access memory devices; a corresponding plurality of address calculators each connected to one of the random access memory devices; an address bus so connected in parallel to all of the address calculators that each address calculator receives the same address from the address bus; a data bus connected to all of the random access memory devices; and an address controller connected to provide to the address calculators control data from which each address calculator can calculate whether or not to pass the address to the random access memory device to which the address calculator is connected for the transfer of data between random access memory device and the data bus.
The invention further provides a method of testing a circuit comprising plural programmable logic devices which can be reprogrammed n-circuit, the method comprising programming one programmable logic device to execute a short circuit test by selecting at least three adjacent pins of the logic device as outputs, setting the outputs on the three selected pins at a high voltage, switching off the middle of the three pins, setting the outputs on the other two pins at a low voltage, selecting the middle of the three pins as an input, and examining the voltage on the middle pin.
The above and further features of the invention are set forthwith with particularity in the apended claims and together with advantages thereof will become clearer from consideration of the following details description of an exemplary embodiment of the invention given with reference to the accompanying drawings.